Static Random Access Memories (SRAMs) are widely used high speed memory devices. The operation of SRAMs is well known and therefore is only briefly described herein. FIG. 1 illustrates a block diagram of a conventional SRAM 110. The controller 122 initiates a memory operation by asserting a chip enable signal 101 and supplying address signals A0-An (corresponding to 2.sup.N+1 memory locations) designating the address of a memory location where the operation is to be performed. If the memory operation is a write operation, the controller 122 supplies the data to be written to the addressed memory location via the bi-directional input/output lines I/O0-I/OK (corresponding to K+1 bit memory words). If the memory operation is a read operation, the stored information from the addressed location is read out from the same bi-directional input/output lines I/O0-I/OK. The memory 110 also provides connections for external power supply (VCC) and ground (GND) signals.
The heart of the memory 110 is the memory array 112, which consists of static memory cells, each capable of storing one bit of data, arranged in rows and columns. In the conventional manner, all of the cells in one row are energized for a memory operation (either a read or a write) by a word line WL uniquely associated with that row. A memory operation cannot be performed unless the word line associated with the target row of cells is activated.
At least a subset of the cells in a row (typically all of the cells that store data for one memory word) can be accessed simultaneously for a given memory operation via the bit lines BL. When the memory operation is a read, the bit lines BL are coupled to sense amplifiers in the column I/O 120 that sense the data stored in the corresponding cells of the row whose word line WL is active. When the memory operation is a write the bit lines BL carry the signals used to program the corresponding cells of the row associated with the active word line.
The control circuitry 116 controls the other blocks of the memory 110 in response to the chip enables 101. Depending on the operation to be performed, the control circuitry issues the appropriate control signals 117a, 117b to the decoder 114 and the I/O data circuit 118, respectively.
Regardless of whether the memory operation is a write or a read, the decoder 114 decodes the address signals A0-AN and activates the word line WL of the row that includes the memory word that is the target of the current memory operation.
If the operation is a write, the I/O data circuitry 118 buffers the input data signals I/O0-I/OK and outputs the buffered data to the column I/O 120 via the bidirectional data bus 119. The column I/O 120 then latches the input signals in parallel onto the corresponding bit lines BL0-BLK. The signals on the bit lines BL0-BLK are used to program the cells composing the word whose word line was activated for the current operation by the decoder 114.
If the operation is a read, sense amplifiers (SA) in the column I/O 120 sense the signals on the respective bit lines BL, convert the sensed signals into binary (e.g., high or low) voltages that represent the programmed state of the addressed word and output the word's bit values to the I/O data circuit via the bi-directional bus 119. The output data are buffered by the I/O data circuit 118 and latched onto the bi-directional data lines I/O0-I/OK for use by the controller 122.
In conventional SRAM devices the address at which a read or write operation is to be performed can arrive one or two clock cycles after the control signal initiating the write or read operation. These memory devices typically require one to two idle cycles between a read operation and a write operation. These devices cannot perform a read directly followed by a write or a write directly followed by a read. Zero bus turnaround (ZBT) SRAM's allow for write and read operations to be performed consecutively without requiring an idle cycle to switch from read to write, or from write to read.
In a conventional ZBT SRAM device there are four fixed patterns of read and write operations that the memory controller must adhere to. The first mode is a read operation followed by a write operation. The second mode is two read operations followed by two write operations. The third mode is three read operations followed by three write operations. The fourth mode is four read operations followed by four write operations. The inflexibility of requiring the controller to adhere to these four fixed modes of operation can limit memory usage.
A further drawback of conventional four mode memory devices is that if a series of read and write operations are attempted that do not adhere to one of the four pre-defined modes this can create errors which can cause a system to crash. Also conventional four mode memory devices may require an asynchronous reset to ensure that the memory device begins operation in a known state. Failure to provide the asynchronous reset can cause such memory devices to enter into an unknown state and thus require the device to be subsequently reset. For example, if the clock signal arrives before control signals are stable the device can be placed into an unknown state.
There is therefore a need for an improved memory controller to overcome these and other problems of the prior art.